patch-2.4.4 linux/arch/s390x/kernel/entry.S
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- Lines: 416
- Date:
Wed Apr 11 19:02:29 2001
- Orig file:
v2.4.3/linux/arch/s390x/kernel/entry.S
- Orig date:
Fri Mar 2 11:12:06 2001
diff -u --recursive --new-file v2.4.3/linux/arch/s390x/kernel/entry.S linux/arch/s390x/kernel/entry.S
@@ -9,56 +9,53 @@
* Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com),
*/
+#define ASSEMBLY
+
#include <linux/sys.h>
#include <linux/linkage.h>
#include <linux/config.h>
#include <asm/lowcore.h>
#include <asm/errno.h>
-#define ASSEMBLY
#include <asm/smp.h>
-#include <asm/s390-regs-common.h>
+#include <asm/ptrace.h>
/*
- * stack layout for the system_call stack entry
- * Martin please don't modify these back to hard coded values
- * You know how bad I'm at mental arithmetic DJB & it gives
- * me grief when I modify the pt_regs
+ * Stack layout for the system_call stack entry.
+ * The first few entries are identical to the user_regs_struct.
*/
SP_PTREGS = STACK_FRAME_OVERHEAD
-SP_PSW = SP_PTREGS
-SP_R0 = (SP_PSW+PSW_MASK_SIZE+PSW_ADDR_SIZE)
-SP_R1 = (SP_R0+GPR_SIZE)
-SP_R2 = (SP_R1+GPR_SIZE)
-SP_R3 = (SP_R2+GPR_SIZE)
-SP_R4 = (SP_R3+GPR_SIZE)
-SP_R5 = (SP_R4+GPR_SIZE)
-SP_R6 = (SP_R5+GPR_SIZE)
-SP_R7 = (SP_R6+GPR_SIZE)
-SP_R8 = (SP_R7+GPR_SIZE)
-SP_R9 = (SP_R8+GPR_SIZE)
-SP_RA = (SP_R9+GPR_SIZE)
-SP_RB = (SP_RA+GPR_SIZE)
-SP_RC = (SP_RB+GPR_SIZE)
-SP_RD = (SP_RC+GPR_SIZE)
-SP_RE = (SP_RD+GPR_SIZE)
-SP_RF = (SP_RE+GPR_SIZE)
-SP_AREGS = (SP_RF+GPR_SIZE)
-SP_ORIG_R2 = (SP_AREGS+(NUM_ACRS*ACR_SIZE))
+SP_PSW = STACK_FRAME_OVERHEAD + PT_PSWMASK
+SP_R0 = STACK_FRAME_OVERHEAD + PT_GPR0
+SP_R1 = STACK_FRAME_OVERHEAD + PT_GPR1
+SP_R2 = STACK_FRAME_OVERHEAD + PT_GPR2
+SP_R3 = STACK_FRAME_OVERHEAD + PT_GPR3
+SP_R4 = STACK_FRAME_OVERHEAD + PT_GPR4
+SP_R5 = STACK_FRAME_OVERHEAD + PT_GPR5
+SP_R6 = STACK_FRAME_OVERHEAD + PT_GPR6
+SP_R7 = STACK_FRAME_OVERHEAD + PT_GPR7
+SP_R8 = STACK_FRAME_OVERHEAD + PT_GPR8
+SP_R9 = STACK_FRAME_OVERHEAD + PT_GPR9
+SP_R10 = STACK_FRAME_OVERHEAD + PT_GPR10
+SP_R11 = STACK_FRAME_OVERHEAD + PT_GPR11
+SP_R12 = STACK_FRAME_OVERHEAD + PT_GPR12
+SP_R13 = STACK_FRAME_OVERHEAD + PT_GPR13
+SP_R14 = STACK_FRAME_OVERHEAD + PT_GPR14
+SP_R15 = STACK_FRAME_OVERHEAD + PT_GPR15
+SP_AREGS = STACK_FRAME_OVERHEAD + PT_ACR0
+SP_ORIG_R2 = STACK_FRAME_OVERHEAD + PT_ORIGGPR2
+/* Now the additional entries */
SP_TRAP = (SP_ORIG_R2+GPR_SIZE)
#if CONFIG_REMOTE_DEBUG
SP_CRREGS = (SP_TRAP+4)
/* fpu registers are saved & restored by the gdb stub itself */
SP_FPC = (SP_CRREGS+(NUM_CRS*CR_SIZE))
SP_FPRS = (SP_FPC+FPC_SIZE+FPC_PAD_SIZE)
-/* SP_PGM_OLD_ILC etc are not part of pt_regs & they are not
- defined in ptrace.h but space is needed for this too */
SP_PGM_OLD_ILC= (SP_FPRS+(NUM_FPRS*FPR_SIZE))
#else
SP_PGM_OLD_ILC= (SP_TRAP+4)
#endif
-SP_SVC_STEP = (SP_PGM_OLD_ILC+4)
-SP_SIZE = (SP_SVC_STEP+4)
+SP_SIZE = (SP_PGM_OLD_ILC+4)
/*
* these defines are offsets into the thread_struct
*/
@@ -72,6 +69,8 @@
_TSS_ERROR = (_TSS_PROT+8)
_TSS_TRAP = (_TSS_ERROR+4)
_TSS_PER = (_TSS_TRAP+4)
+_TSS_IEEE = (_TSS_PER+72)
+_TSS_FLAGS = (_TSS_IEEE+8)
/*
* these are offsets into the task-struct.
@@ -83,31 +82,6 @@
tsk_ptrace = 40
processor = 100
-/* PSW related defines */
-disable = 0xFC
-enable = 0x03
-daton = 0x04
-
-
-#if 0
-/* some code left lying around in case we need a
- * printk for debugging purposes
- */
- sysc_printk: .long printk
- sysc_msg: .string "<2>r15 %X\n"
- .align 4
-
-# basr %r13,0
- lg %r0,SP_PSW+8(%r15)
- sllg %r0,%r0,1
- chi %r0,0
- jnz sysc_dn
- la %r2,sysc_msg-sysc_lit(%r13)
- lgr %r3,%r15
- brasl %r14,sysc_printk
-sysc_dn:
-#endif
-
/*
* Register usage in interrupt handlers:
* R9 - pointer to current task structure
@@ -116,38 +90,41 @@
* R15 - kernel stack pointer
*/
-#define SAVE_ALL(psworg) \
- stmg %r14,%r15,__LC_SAVE_AREA ; \
- stam %a2,%a4,__LC_SAVE_AREA+16 ; \
- tm psworg+1,0x01 ; /* test problem state bit */ \
- jz 0f ; /* skip stack setup save */ \
- lg %r15,__LC_KERNEL_STACK ; /* problem state -> load ksp */ \
- slr %r14,%r14 ; \
- sar %a2,%r14 ; /* set ac.reg. 2 to primary space */ \
- lhi %r14,1 ; \
- sar %a4,%r14 ; /* set access reg. 4 to home space */ \
-0: aghi %r15,-SP_SIZE ; /* make room for registers & psw */ \
- nill %r15,0xfff8 ; /* align stack pointer to 8 */ \
- stmg %r0,%r14,SP_R0(%r15) ; /* store gprs 0-14 to kernel stack */ \
- stg %r2,SP_ORIG_R2(%r15) ; /* store original content of gpr 2 */ \
- mvc SP_RE(16,%r15),__LC_SAVE_AREA ; /* move R15 to stack */ \
- stam %a0,%a15,SP_AREGS(%r15) ; /* store access registers to kst. */\
- mvc SP_AREGS+8(12,%r15),__LC_SAVE_AREA+16 ; /* store ac. regs */ \
- mvc SP_PSW(16,%r15),psworg; /* move user PSW to stack */ \
- lhi %r0,psworg ; /* store trap indication */ \
- st %r0,SP_TRAP(%r15) ; \
- xc 0(8,%r15),0(%r15) ; /* clear back chain */
-
-#define RESTORE_ALL \
- mvc __LC_RETURN_PSW(16),SP_PSW(%r15) ; /* move user PSW to lowcore */ \
- lam %a0,%a15,SP_AREGS(%r15) ; /* load the access registers */ \
- lmg %r0,%r15,SP_R0(%r15) ; /* load gprs 0-15 of user */ \
- ni __LC_RETURN_PSW+1,0xfd ; /* clear wait state bit */ \
- lpswe __LC_RETURN_PSW /* back to caller */
+ .macro SAVE_ALL psworg # system entry macro
+ stmg %r14,%r15,__LC_SAVE_AREA
+ stam %a2,%a4,__LC_SAVE_AREA+16
+ tm \psworg+1,0x01 # test problem state bit
+ jz 0f # skip stack setup save
+ lg %r15,__LC_KERNEL_STACK # problem state -> load ksp
+ slr %r14,%r14
+ sar %a2,%r14 # set ac.reg. 2 to primary space
+ lhi %r14,1
+ sar %a4,%r14 # set access reg. 4 to home space
+0: aghi %r15,-SP_SIZE # make room for registers & psw
+ nill %r15,0xfff8 # align stack pointer to 8
+ stmg %r0,%r14,SP_R0(%r15) # store gprs 0-14 to kernel stack
+ stg %r2,SP_ORIG_R2(%r15) # store original content of gpr 2
+ mvc SP_R14(16,%r15),__LC_SAVE_AREA # move R15 to stack
+ stam %a0,%a15,SP_AREGS(%r15) # store access registers to kst.
+ mvc SP_AREGS+8(12,%r15),__LC_SAVE_AREA+16 # store ac. regs
+ mvc SP_PSW(16,%r15),\psworg # move user PSW to stack
+ lhi %r0,\psworg # store trap indication
+ st %r0,SP_TRAP(%r15)
+ xc 0(8,%r15),0(%r15) # clear back chain
+ .endm
+
+ .macro RESTORE_ALL # system exit macro
+ mvc __LC_RETURN_PSW(16),SP_PSW(%r15) # move user PSW to lowcore
+ lam %a0,%a15,SP_AREGS(%r15) # load the access registers
+ lmg %r0,%r15,SP_R0(%r15) # load gprs 0-15 of user
+ ni __LC_RETURN_PSW+1,0xfd # clear wait state bit
+ lpswe __LC_RETURN_PSW # back to caller
+ .endm
-#define GET_CURRENT /* load pointer to task_struct to R9 */ \
- lghi %r9,-16384 ; \
+ .macro GET_CURRENT
+ lghi %r9,-16384 # load pointer to task_struct to %r9
ngr %r9,15
+ .endm
/*
@@ -162,7 +139,7 @@
lg %r4,_TSS_PTREGS(%r3)
tm SP_PSW-SP_PTREGS(%r4),0x40 # is the new process using per ?
jz resume_noper # if not we're fine
- stctg %r9,%r11,48(%r15) # We are using per stuff
+ stctg %c9,%c11,48(%r15) # We are using per stuff
clc _TSS_PER(24,%r3),48(%r15)
je resume_noper # we got away without bashing TLB's
lctlg %c9,%c11,_TSS_PER(%r3) # Nope we didn't
@@ -191,10 +168,11 @@
.globl system_call
system_call:
- SAVE_ALL(__LC_SVC_OLD_PSW)
- xc SP_SVC_STEP(4,%r15),SP_SVC_STEP(%r15)
+ SAVE_ALL __LC_SVC_OLD_PSW
+ mvi SP_PGM_OLD_ILC(%r15),1 # mark PGM_OLD_ILC as invalid
pgm_system_call:
- larl %r1,sys_call_table
+ GET_CURRENT # load pointer to task_struct to R9
+ larl %r7,sys_call_table
llgc %r8,__LC_SVC_INT_CODE+1 # get svc number from lowcore
stosm 48(%r15),0x03 # reenable interrupts
sll %r8,3
@@ -202,8 +180,7 @@
jo sysc_noemu
la %r8,4(%r8) # use 31 bit emulation system calls
sysc_noemu:
- GET_CURRENT # load pointer to task_struct to R9
- lgf %r8,0(%r8,%r1) # load address of system call routine
+ lgf %r8,0(%r8,%r7) # load address of system call routine
tm tsk_ptrace+7(%r9),0x02 # PT_TRACESYS
jnz sysc_tracesys
basr %r14,%r8 # call sys_xxxx
@@ -212,7 +189,6 @@
# changing anything here !!
sysc_return:
- GET_CURRENT # load pointer to task_struct to R9
tm SP_PSW+1(%r15),0x01 # returning to user ?
jno sysc_leave # no-> skip bottom half, resched & signal
#
@@ -228,12 +204,12 @@
lg %r0,need_resched(%r9) # get need_resched from task_struct
ltgr %r0,%r0
jnz sysc_reschedule
- icm %r0,15,sigpending(%r9) # get sigpending from task_struct
+ icm %r0,15,sigpending(%r9) # get sigpending from task_struct
jnz sysc_signal_return
sysc_leave:
- icm %r0,15,SP_SVC_STEP(%r15) # get sigpending from task_struct
- jnz pgm_svcret
- stnsm 48(%r15),disable # disable I/O and ext. interrupts
+ tm SP_PGM_OLD_ILC(%r15),0xff
+ jz pgm_svcret
+ stnsm 48(%r15),0xfc # disable I/O and ext. interrupts
RESTORE_ALL
#
@@ -667,7 +643,7 @@
je pgm_svcper
# no interesting special case, ignore PER event
lm %r13,%r15,__LC_SAVE_AREA
- lpsw __LC_PGM_OLD_PSW
+ lpswe __LC_PGM_OLD_PSW
# it was a single stepped SVC that is causing all the trouble
pgm_svcper:
tm __LC_SVC_OLD_PSW+1,0x01 # test problem state bit
@@ -681,7 +657,7 @@
nill %r15,0xfff8 # align stack pointer to 8
stmg %r0,%r14,SP_R0(%r15) # store gprs 0-14 to kernel stack
stg %r2,SP_ORIG_R2(%r15) # store original content of gpr 2
- mvc SP_RE(16,%r15),__LC_SAVE_AREA # move R14-R15 to stack
+ mvc SP_R14(16,%r15),__LC_SAVE_AREA # move R14-R15 to stack
stam %a0,%a15,SP_AREGS(%r15) # store access registers to kst.
mvc SP_AREGS+8(12,%r15),__LC_SAVE_AREA+16 # store ac. regs
mvc SP_PSW(16,%r15),__LC_PGM_OLD_PSW # move user PSW to stack
@@ -689,14 +665,13 @@
st %r0,SP_TRAP(%r15)
xc 0(8,%r15),0(%r15) # clear back chain
- mvi SP_SVC_STEP(%r15),1 # make SP_SVC_STEP nonzero
mvc SP_PGM_OLD_ILC(4,%r15),__LC_PGM_ILC # save program check information
j pgm_system_call # now do the svc
pgm_svcret:
lhi %r0,__LC_PGM_OLD_PSW # set trap indication back to pgm_chk
st %r0,SP_TRAP(%r15)
llgh %r7,SP_PGM_OLD_ILC(%r15) # get ilc from stack
- xc SP_SVC_STEP(4,%r15),SP_SVC_STEP(%r15)
+ mvi SP_PGM_OLD_ILC(%r15),1 # mark PGM_OLD_ILC as invalid
j pgm_no_sv
pgm_sv:
tm __LC_PGM_OLD_PSW+1,0x01 # test problem state bit
@@ -710,15 +685,16 @@
nill %r15,0xfff8 # align stack pointer to 8
stmg %r0,%r14,SP_R0(%r15) # store gprs 0-14 to kernel stack
stg %r2,SP_ORIG_R2(%r15) # store original content of gpr 2
- mvc SP_RE(16,%r15),__LC_SAVE_AREA # move R14-R15 to stack
+ mvc SP_R14(16,%r15),__LC_SAVE_AREA # move R14-R15 to stack
stam %a0,%a15,SP_AREGS(%r15) # store access registers to kst.
mvc SP_AREGS+8(12,%r15),__LC_SAVE_AREA+16 # store ac. regs
mvc SP_PSW(16,%r15),__LC_PGM_OLD_PSW # move user PSW to stack
lhi %r0,__LC_PGM_OLD_PSW # store trap indication
st %r0,SP_TRAP(%r15)
xc 0(8,%r15),0(%r15) # clear back chain
- xc SP_SVC_STEP(4,%r15),SP_SVC_STEP(%r15)
- llgh %r7,__LC_PGM_ILC # load instruction length
+ mvi SP_PGM_OLD_ILC(%r15),1 # mark PGM_OLD_ILC as invalid
+ llgh %r7,__LC_PGM_ILC # load instruction length
+ GET_CURRENT
pgm_no_sv:
llgh %r8,__LC_PGM_INT_CODE # N.B. saved int code used later KEEP it
stosm 48(%r15),0x03 # reenable interrupts
@@ -726,8 +702,8 @@
nr %r3,%r8 # clear per-event-bit & move to r3
je pgm_dn # none of Martins exceptions occurred bypass
sll %r3,3
- larl %r9,pgm_check_table
- lg %r9,0(%r3,%r9) # load address of handler routine
+ larl %r1,pgm_check_table
+ lg %r1,0(%r3,%r1) # load address of handler routine
srl %r3,3
la %r2,SP_PTREGS(%r15) # address of register-save area
chi %r3,0x4 # protection-exception ?
@@ -735,7 +711,7 @@
lg %r5,SP_PSW+8(15) # load psw addr
slgr %r5,%r7 # substract ilc from psw
stg %r5,SP_PSW+8(15) # store corrected psw addr
-pgm_go: basr %r14,%r9 # branch to interrupt-handler
+pgm_go: basr %r14,%r1 # branch to interrupt-handler
pgm_dn: nill %r8,0x80 # check for per exception
je sysc_return
la %r2,SP_PTREGS(15) # address of register-save area
@@ -747,17 +723,17 @@
*/
.globl io_int_handler
io_int_handler:
- SAVE_ALL(__LC_IO_OLD_PSW)
+ SAVE_ALL __LC_IO_OLD_PSW
+ GET_CURRENT # load pointer to task_struct to R9
la %r2,SP_PTREGS(%r15) # address of register-save area
llgh %r3,__LC_SUBCHANNEL_NR # load subchannel number
- llgf %r4,__LC_IO_INT_PARM # load interruption parm
- llgf %r5,__LC_IO_INT_WORD # load interruption word
+ llgf %r4,__LC_IO_INT_PARM # load interuption parm
+ llgf %r5,__LC_IO_INT_WORD # load interuption word
brasl %r14,do_IRQ # call standard irq handler
io_return:
- GET_CURRENT # load pointer to task_struct to R9
tm SP_PSW+1(%r15),0x01 # returning to user ?
- jz io_leave # no-> skip resched & signal
+ jno io_leave # no-> skip resched & signal
stosm 48(%r15),0x03 # reenable interrupts
#
# check, if bottom-half has to be done
@@ -775,7 +751,7 @@
icm %r0,15,sigpending(%r9) # get sigpending from task_struct
jnz io_signal_return
io_leave:
- stnsm 48(%r15),disable # disable I/O and ext. interrupts
+ stnsm 48(%r15),0xfc # disable I/O and ext. interrupts
RESTORE_ALL
#
@@ -807,34 +783,35 @@
*/
.globl ext_int_handler
ext_int_handler:
- SAVE_ALL(__LC_EXT_OLD_PSW)
+ SAVE_ALL __LC_EXT_OLD_PSW
+ GET_CURRENT # load pointer to task_struct to R9
la %r2,SP_PTREGS(%r15) # address of register-save area
llgh %r3,__LC_EXT_INT_CODE # error code
lgr %r1,%r3 # calculate index = code & 0xff
nill %r1,0xff
sll %r1,3
- larl %r9,ext_int_hash
- lg %r9,0(%r1,%r9) # get first list entry for hash value
- ltgr %r9,%r9 # == NULL ?
+ larl %r4,ext_int_hash
+ lg %r4,0(%r1,%r4) # get first list entry for hash value
+ ltgr %r4,%r4 # == NULL ?
jz io_return # yes, nothing to do, exit
ext_int_loop:
- ch %r3,16(%r9) # compare external interrupt code
+ ch %r3,16(%r4) # compare external interrupt code
je ext_int_found
- lg %r9,0(%r9) # next list entry
- ltgr %r9,%r9
+ lg %r4,0(%r4) # next list entry
+ ltgr %r4,%r4
jnz ext_int_loop
j io_return
ext_int_found:
- lg %r9,8(%r9) # get handler address
+ lg %r4,8(%r4) # get handler address
larl %r14,io_return
- br %r9 # branch to ext call handler
+ br %r4 # branch to ext call handler
/*
* Machine check handler routines
*/
.globl mcck_int_handler
mcck_int_handler:
- SAVE_ALL(__LC_MCK_OLD_PSW)
+ SAVE_ALL __LC_MCK_OLD_PSW
brasl %r14,s390_do_machine_check
mcck_return:
RESTORE_ALL
@@ -848,7 +825,7 @@
lg %r15,__LC_KERNEL_STACK # load ksp
lctlg %c0,%c15,__LC_CREGS_SAVE_AREA # get new ctl regs
lam %a0,%a15,__LC_AREGS_SAVE_AREA
- stosm 0(%r15),daton # now we can turn dat on
+ stosm 0(%r15),0x04 # now we can turn dat on
lmg %r6,%r15,48(%r15) # load registers from clone
jg start_secondary
#else
FUNET's LINUX-ADM group, linux-adm@nic.funet.fi
TCL-scripts by Sam Shen (who was at: slshen@lbl.gov)