patch-2.4.22 linux-2.4.22/arch/mips/momentum/ocelot_g/pci.c

• Lines: 177
• Date: 2003-08-25 04:44:40.000000000 -0700
• Orig file: linux-2.4.21/arch/mips/momentum/ocelot_g/pci.c
• Orig date: 2002-11-28 15:53:10.000000000 -0800

diff -urN linux-2.4.21/arch/mips/momentum/ocelot_g/pci.c linux-2.4.22/arch/mips/momentum/ocelot_g/pci.c
@@ -34,8 +34,6 @@
 
 #include <linux/init.h>
 
-#ifdef CONFIG_PCI
-
 #define SELF 0
 #define MASTER_ABORT_BIT 0x100
 
@@ -61,7 +59,6 @@
 					     int offset, u16 val);
 static int galileo_pcibios_write_config_dword(struct pci_dev *dev,
 					      int offset, u32 val);
-static void galileo_pcibios_set_master(struct pci_dev *dev);
 
 /*
  *  General-purpose PCI functions.
@@ -345,128 +342,6 @@
 	return PCIBIOS_SUCCESSFUL;
 }
 
-static void galileo_pcibios_set_master(struct pci_dev *dev)
-{
-	u16 cmd;
-
-	galileo_pcibios_read_config_word(dev, PCI_COMMAND, &cmd);
-	cmd |= PCI_COMMAND_MASTER;
-	galileo_pcibios_write_config_word(dev, PCI_COMMAND, cmd);
-}
-
-/*  Externally-expected functions.  Do not change function names  */
-
-int pcibios_enable_resources(struct pci_dev *dev)
-{
-	u16 cmd, old_cmd;
-	u8 tmp1;
-	int idx;
-	struct resource *r;
-
-	galileo_pcibios_read_config_word(dev, PCI_COMMAND, &cmd);
-	old_cmd = cmd;
-	for (idx = 0; idx < 6; idx++) {
-		r = &dev->resource[idx];
-		if (!r->start && r->end) {
-			printk(KERN_ERR
-			       "PCI: Device %s not available because of "
-			       "resource collisions\n", dev->slot_name);
-			return -EINVAL;
-		}
-		if (r->flags & IORESOURCE_IO)
-			cmd |= PCI_COMMAND_IO;
-		if (r->flags & IORESOURCE_MEM)
-			cmd |= PCI_COMMAND_MEMORY;
-	}
-	if (cmd != old_cmd) {
-		galileo_pcibios_write_config_word(dev, PCI_COMMAND, cmd);
-	}
-
-	/*
-	 * Let's fix up the latency timer and cache line size here.  Cache
-	 * line size = 32 bytes / sizeof dword (4) = 8.
-	 * Latency timer must be > 8.  32 is random but appears to work.
-	 */
-	galileo_pcibios_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp1);
-	if (tmp1 != 8) {
-		printk(KERN_WARNING "PCI setting cache line size to 8 from "
-		       "%d\n", tmp1);
-		galileo_pcibios_write_config_byte(dev, PCI_CACHE_LINE_SIZE,
-						  8);
-	}
-	galileo_pcibios_read_config_byte(dev, PCI_LATENCY_TIMER, &tmp1);
-	if (tmp1 < 32) {
-		printk(KERN_WARNING "PCI setting latency timer to 32 from %d\n",
-		       tmp1);
-		galileo_pcibios_write_config_byte(dev, PCI_LATENCY_TIMER,
-						  32);
-	}
-
-	return 0;
-}
-
-int pcibios_enable_device(struct pci_dev *dev)
-{
-	return pcibios_enable_resources(dev);
-}
-
-void pcibios_update_resource(struct pci_dev *dev, struct resource *root,
-			     struct resource *res, int resource)
-{
-	u32 new, check;
-	int reg;
-
-	return;
-
-#if 0
-	new = res->start | (res->flags & PCI_REGION_FLAG_MASK);
-	if (resource < 6) {
-		reg = PCI_BASE_ADDRESS_0 + 4 * resource;
-	} else if (resource == PCI_ROM_RESOURCE) {
-		res->flags |= PCI_ROM_ADDRESS_ENABLE;
-		reg = dev->rom_base_reg;
-	} else {
-		/*
-		 * Somebody might have asked allocation of a non-standard
-		 * resource
-		 */
-		return;
-	}
-
-	pci_write_config_dword(dev, reg, new);
-	pci_read_config_dword(dev, reg, &check);
-	if ((new ^ check) &
-	    ((new & PCI_BASE_ADDRESS_SPACE_IO) ? PCI_BASE_ADDRESS_IO_MASK :
-	     PCI_BASE_ADDRESS_MEM_MASK)) {
-		printk(KERN_ERR "PCI: Error while updating region "
-		       "%s/%d (%08x != %08x)\n", dev->slot_name, resource,
-		       new, check);
-	}
-#endif
-}
-
-void pcibios_align_resource(void *data, struct resource *res,
-			    unsigned long size, unsigned long align)
-{
-	struct pci_dev *dev = data;
-
-	if (res->flags & IORESOURCE_IO) {
-		unsigned long start = res->start;
-
-		/* We need to avoid collisions with `mirrored' VGA ports
-		   and other strange ISA hardware, so we always want the
-		   addresses kilobyte aligned.  */
-		if (size > 0x100) {
-			printk(KERN_ERR "PCI: I/O Region %s/%d too large"
-			       " (%ld bytes)\n", dev->slot_name,
-			        dev->resource - res, size);
-		}
-
-		start = (start + 1024 - 1) & ~(1024 - 1);
-		res->start = start;
-	}
-}
-
 struct pci_ops galileo_pci_ops = {
 	galileo_pcibios_read_config_byte,
 	galileo_pcibios_read_config_word,
@@ -534,9 +409,6 @@
 	GT_WRITE(PCI_1P2P_CONFIGURATION, regData);
 }
 
-#define PCI0_STATUS_COMMAND_REG                 0x4
-#define PCI1_STATUS_COMMAND_REG                 0x84
-
 void __init pcibios_init(void)
 {
 	/* Reset PCI I/O and PCI MEM values */
@@ -549,20 +421,7 @@
 	pci_scan_bus(1, &galileo_pci_ops, NULL);
 }
 
-/*
- * for parsing "pci=" kernel boot arguments.
- */
-char *pcibios_setup(char *str)
-{
-        printk(KERN_INFO "rr: pcibios_setup\n");
-        /* Nothing to do for now.  */
-
-        return str;
-}
-
 unsigned __init int pcibios_assign_all_busses(void)
 {
 	return 1;
 }
-
-#endif	/* CONFIG_PCI */