patch-2.1.124 linux/arch/i386/kernel/io_apic.c

• Lines: 138
• Date: Sun Oct 4 11:54:24 1998
• Orig file: v2.1.123/linux/arch/i386/kernel/io_apic.c
• Orig date: Mon Sep 28 10:51:33 1998

diff -u --recursive --new-file v2.1.123/linux/arch/i386/kernel/io_apic.c linux/arch/i386/kernel/io_apic.c
@@ -129,7 +129,7 @@
 
 /*
  * We disable IO-APIC IRQs by setting their 'destination CPU mask' to
- * zero. Trick, trick.
+ * zero. Trick by Ramesh Nalluri.
  */
 static inline void disable_IO_APIC_irq(unsigned int irq)
 {
@@ -291,9 +291,22 @@
 }
 
 /*
+ * Unclear documentation on what a "conforming ISA interrupt" means.
+ *
+ * Should we, or should we not, take the ELCR register into account?
+ * It's part of the EISA specification, but maybe it should only be
+ * used if the interrupt is actually marked as EISA?
+ *
+ * Oh, well. Don't do it until somebody tells us what the right thing
+ * to do is..
+ */
+#undef USE_ELCR_TRIGGER_LEVEL
+#ifdef USE_ELCR_TRIGGER_LEVEL
+
+/*
  * ISA Edge/Level control register, ELCR
  */
-static int __init ISA_ELCR(unsigned int irq)
+static int __init EISA_ELCR(unsigned int irq)
 {
 	if (irq < 16) {
 		unsigned int port = 0x4d0 + (irq >> 3);
@@ -303,37 +316,15 @@
 	return 0;
 }	
 
-/*
- * ISA interrupts can be:
- *  - level triggered, active low (ELCR = 1)
- *  - edge triggered, active high (ELCR = 0)
- *  - edge triggered, active low (magic irq 8)
- */
-static int __init default_ISA_trigger(int idx)
-{
-	unsigned int irq = mp_irqs[idx].mpc_dstirq;
-
-	if (irq == 8)
-		return 0;
-	return ISA_ELCR(irq);
-}
+#define default_ISA_trigger(idx)	(EISA_ELCR(mp_irqs[idx].mpc_dstirq))
+#define default_ISA_polarity(idx)	(0)
 
-static int __init default_ISA_polarity(int idx)
-{
-	unsigned int irq = mp_irqs[idx].mpc_dstirq;
+#else
 
-	if (irq == 8)
-		return 1;
-	return ISA_ELCR(irq);
-}
+#define default_ISA_trigger(idx)	(0)
+#define default_ISA_polarity(idx)	(0)
 
-/*
- * There are broken mptables which register ISA+high-active+level IRQs,
- * these are illegal and are converted here to ISA+high-active+edge
- * IRQ sources. Careful, ISA+low-active+level is another broken entry
- * type, it represents PCI IRQs 'embedded into an ISA bus', they have
- * to be accepted. Yes, ugh.
- */
+#endif
 
 static int __init MPBIOS_polarity(int idx)
 {
@@ -453,36 +444,14 @@
 	return trigger;
 }
 
-static int __init trigger_flag_broken(int idx)
-{
-	int bus = mp_irqs[idx].mpc_srcbus;
-	int polarity = MPBIOS_polarity(idx);
-	int trigger = MPBIOS_trigger(idx);
-
-	if ( (mp_bus_id_to_type[bus] == MP_BUS_ISA) &&
-		(polarity == 0) /* active-high */ &&
-		(trigger == 1) /* level */ )
-
-		return 1; /* broken */
-
-	return 0;
-}
-
 static inline int irq_polarity(int idx)
 {
-	/*
-	 * There are no known BIOS bugs wrt polarity.                yet.
-	 */
 	return MPBIOS_polarity(idx);
 }
 
 static inline int irq_trigger(int idx)
 {
-	int trigger = MPBIOS_trigger(idx);
-
-	if (trigger_flag_broken(idx))
-		trigger = 0;
-	return trigger;
+	return MPBIOS_trigger(idx);
 }
 
 static int __init pin_2_irq(int idx, int pin)
@@ -617,9 +586,6 @@
 
 		bus = mp_irqs[idx].mpc_srcbus;
 
-		if (trigger_flag_broken (idx))
-			printk("broken BIOS, changing pin %d to edge\n", pin);
-
 		io_apic_write(0x11+2*pin, *(((int *)&entry)+1));
 		io_apic_write(0x10+2*pin, *(((int *)&entry)+0));
 	}
@@ -882,9 +848,9 @@
 		if (!IO_APIC_IRQ(i))
 			continue;
 
-		mp_irqs[pos].mpc_irqtype = 0;
-		mp_irqs[pos].mpc_irqflag = 0;
-		mp_irqs[pos].mpc_srcbus = 0;
+		mp_irqs[pos].mpc_irqtype = mp_INT;
+		mp_irqs[pos].mpc_irqflag = 0;		/* default */
+		mp_irqs[pos].mpc_srcbus = MP_BUS_ISA;
 		mp_irqs[pos].mpc_srcbusirq = i;
 		mp_irqs[pos].mpc_dstapic = 0;
 		mp_irqs[pos].mpc_dstirq = i;